Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of a storage element—a magnetic tunnel junction, i.e., an MTJ. The elements are formed from two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the magnetization polarity of the other “writable” plate will change to match that of a sufficiently strong external field. A memory device is built from a grid of such “cells”.
Reading is accomplished by measuring the electrical resistance of the cell. A particular cell is conventionally selected by powering an associated transistor which switches current from a supply line through the cell to ground. Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the orientation of the fields in the two plates. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the polarity of the writable plate. Conventionally, if the two plates have the same polarity this is considered a state “0”, whereas if the two plates are of opposite polarity the resistance will be higher and is considered a state “1”.
One significant determinant of a memory system's cost is the density of the components. Smaller components, and fewer components per “cell,” mean that more “cells” may be packed onto a single chip, which in turn means more chips can be produced at once from a single silicon wafer and fabricated at lower cost and improved yield.
In addition, the manufacturing process flow affects cost, with more mask processes contributing to increased overall manufacturing costs. When fabrication of conventional MRAM requires a number of mask processes dedicated solely to the fabrication of the magnetic tunnel junction (MTJ) structure, costs are further increased. Because processing cost is a serious consideration in implementing integration of features in an integrated circuit device, any improvement in the design and process flow that eliminates masks and associated processes is advantageous. A difference in one mask process can save significant costs. Accordingly, there is a need for improved methods for integrating MRAM fabrication in the semiconductor manufacturing process flow. Moreover, any design that relaxes alignment of critical dimension features would be desirable.